Verilog simulation you can put in a script

Run one example:

cd examples\01_counter
..\..\trsim.exe -top counter_tb -time 5000 counter.v

It prints:

counter: 8-bit loadable up-counter
  ok    after reset = 0
  ok    after 5 counts = 5
  ok    held with en low = 5
  ok    after load 0xA0 = 160
  ok    wrapped past 0xFF = 0
  ok    async reset is immediate = 0
PASS  counter

That run also wrote counter.vcd. Open it in GTKWave, or start trsimgui.exe and open it there. To check all six examples against their recorded output:

cd examples
run_all.ps1

trsim -top my_tb -time 100000 rtl\*.v tb\my_tb.v

The exit code is what a build script should read: 0 ok, 1 compile error, 2 the simulation reported a failure, 3 bad command line. Run trsim -h for the full list of options.

By default trsim interprets the design. It can also compile it to C, which is dramatically faster on a large one — the compiled backend runs a 1361-signal, 598-process system-on-chip at roughly the speed of a commercial simulator and reproduces its output exactly.

trsim -top my_tb -time 100000 -native build\my_tb.c rtl\*.v tb\my_tb.v

Then build my_tb.c with any C compiler and run the result.

The compiled path does not cover the whole language yet. Where it meets something it cannot compile it says so and stops, rather than generating something that would quietly be wrong.

Put $dumpfile("out.vcd"); $dumpvars(0, tb); in the testbench, or pass -vcd out.vcd on the command line. The output is plain IEEE 1364 Annex A VCD, which GTKWave, ModelSim and Verdi all read.

trsimgui.exe includes its own viewer: hierarchy filtering, hex, binary, decimal, octal and ASCII radix, two cursors with a delta readout, edge stepping with rising and falling modifiers, rubber-band zoom, zoom about the pointer, and saved sessions.