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trsim Command Reference

The Tuwa RTL Simulator, version 1.0 (Windows x64)

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Synopsis

trsim                                 launch the windowed front end
trsim [options] file.v [file.v ...]   run in batch and exit

With no arguments trsim starts trsimgui.exe, which must be in the same directory. With arguments it compiles, elaborates and simulates, prints to standard output, and exits with a code that says what happened.

Options

-top <module>

The module to elaborate as the top level. If you do not give one, trsim uses the first module it finds, which is rarely what you want once you have more than one file.

trsim -top my_tb -time 100000 rtl\*.v tb\my_tb.v

-time <n>

How long to simulate, counted in the unit set by -timeunit or by a `timescale in the source. The default is 1000.

The run also stops early if the design calls $finish, which is the usual way a self-checking testbench ends.

-timeunit <ns|us|ms|ps|fs>

The unit -time is expressed in. A `timescale directive in the source takes precedence, so this only applies to designs that do not set one.

trsim -top my_tb -time 500 -timeunit us rtl\*.v tb\my_tb.v

+incdir+<dir>[+<dir>...]

Directories to search for `include files. Several may be given in one option, separated by +, and the option may be repeated.

trsim -top my_tb +incdir+rtl\include+rtl\shared -time 100000 rtl\*.v

-I <dir>

The same thing, one directory per option, for people used to that spelling.

-vcd <out.vcd>

Write a VCD waveform file. You do not need this if the testbench calls $dumpfile and $dumpvars itself, which is the more usual arrangement because it keeps the choice with the design. See the Waveforms manual.

-f <project.tvp>

Read sources and settings from a project file instead of listing them on the command line. This is the same project the windowed front end uses.

-o <report>

Mirror everything trsim prints into a file as well as to standard output. Useful in a regression run where you want the transcript kept.

trsim -q -o run.log -top my_tb -time 100000 rtl\*.v tb\my_tb.v

-q

Quiet. Suppresses the banner. The design's own output is unaffected.

-h, --help

Print the option list and exit.

-native <out.c>

Compile the design to C instead of interpreting it, writing the generated source to <out.c>. Nothing is simulated by this run; you build the C and run that. See the Compiled Backend manual.

trsim -top my_tb -time 100000 -native build\my_tb.c rtl\*.v tb\my_tb.v

Exit codes

Code	Meaning
0	ran to completion, no failures reported
1	compile or link error — nothing was simulated
2	the simulation reported a failure
3	the command line could not be understood

In a batch file:

trsim -q -top my_tb -time 100000 rtl\*.v tb\my_tb.v
if errorlevel 3 echo bad command line & exit /b 3
if errorlevel 2 echo simulation FAILED  & exit /b 2
if errorlevel 1 echo did not compile    & exit /b 1
echo passed

In PowerShell, read $LASTEXITCODE after the call.

Environment variables

These are read by a program built from -native output, not by trsim.exe itself. They let you get a waveform or a trace out of an already-built simulation without regenerating anything.

TRS_VCD=<file>

Write a VCD of every signal to <file>. This works even when the design never calls $dumpfile, which is what makes it useful on a binary somebody handed you.

set TRS_VCD=run.vcd
my_tb_native.exe

TRS_TRACE=<substring>

Print every change of every signal whose hierarchical name contains <substring>, with the time and the new value. The filter is a plain substring match, not a pattern.

set TRS_TRACE=cpu.alu
my_tb_native.exe

Note that signal names carry no brackets, so filtering on mem[ never matches. Filter on the name and read the index from the output.

TRS_STATS=1

Print a summary at the end of the run: how many events were processed, how many signal updates, and where the time went.

TRS_PROGRESS=<n>

Print a progress line every <n> simulated time units. Useful on a long run to see it is still moving.

Reading the output

A normal run prints the files as it compiles them, any warnings, the link step, then the design's own output, then the end-of-simulation line.

Warnings worth attending to:

• Module 'x' has not been defined — an instantiated module was not among the sources. The instance becomes an empty box: its outputs stay undriven and read as z.
• Module 'x' has no pin named 'y' — a port connection names a port the module does not have. That connection is dropped.
• Unresolved external 'x' at link time is the fatal version of the first: the top level itself, or something it needs, is missing.

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